Phase-locked loop ("PLL") circuits have been used for many years and are electronic circuits for locking an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems for the purpose of generating a local clock signal which is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of synchronous data sent by a transmitter in the communication system.
A conventional PLL circuit comprises a phase detector, a filter and a voltage-controlled oscillator ("VCO"). In the conventional PLL circuit, the phase detector compares the incoming reference signal and the output of the VCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the VCO output. The error signal is filtered and applied to the control input of the VCO to produce an output signal that tracks the phase of the reference signal.
A potential problem exists for a PLL circuit used to generate a local clock signal for synchronous reading of a transmitted information stream, when the incoming reference signal is lost or interrupted. The output frequency of the VCO may drift during the absence of the reference signal, potentially causing a receiver to read data in the received information stream out of synchronization.
Several prior art techniques have been devised to provide an in-phase local clock signal during the period of absence or interruption of an incoming reference signal. U.S. Pat. No. 4,972,422 to Steierman, issued on Nov. 20, 1990, described a PLL circuit utilizing multiple reference signals. This prior art circuit can detect a loss of the incoming reference signal and transparently switch over to one of the other reference signals. A disadvantage of the circuit of U.S. Pat. No. 4,972,422 is that it is not applicable to communication systems having a single reference signal.
Another prior art technique utilizes a PLL having a voltage-controlled oscillator which employs a crystal maintained at a constant temperature so that a phase-locked clock signal having minimal drift is provided. A disadvantage of this prior art technique is the high power consumption required to maintain the crystal at the constant temperature.
It is desirable to have a PLL scheme with switchover that could substantially maintain a phase-locked signal upon an absence or interruption of the reference signal. Further, it is desirable that such circuits be of minimal complexity, have low power consumption and utilize inexpensive off the shelf components.